1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an open bit line structure.
2. Description of the Related Art
A bit line sense amplifier of a semiconductor memory device, such as a Dynamic Random Access Memory (DRAM), amplifies a slight signal difference generated in a bit line when a memory cell is accessed and charge sharing occurs between the memory cell and the bit line. Thus, the bit line sense amplifier is a circuit indispensable to the operation of the semiconductor memory device.
In general, a bit line structure of a semiconductor memory device is categorized into an open bit line structure and a folded bit line structure. The open bit line structure includes a bit line and a complimentary bit line (inverted bit line) that extend from a bit line sense amplifier and in opposite directions. The folded bit line structure also includes a bit line and a complementary bit line that extend from a bit line sense amplifier but in the same direction. The bit line and the complementary bit line form a pair of bit lines.
All other things being equal, the semiconductor memory device having an open bit line structure includes more memory cells than one having a folded bit line structure. Accordingly, the open bit line structure is widely used.
FIG. 1 illustrates a semiconductor memory device 5 having an open bit line structure, including a bit line BL and a complementary bit line BLB, which are aligned to left and right sides of sense amplifier blocks SA. The sense amplifier blocks SA constitute a bit line sense amplifier.
Memory cells MC for storing data are arranged in an area where bit lines BL and sub-word lines SWL intersect one another and in an area where complementary bit lines BLB and sub-word lines SWL intersect one another. Each of the memory cells MC includes an NMOS transistor as a cell transistor, and a cell capacitor. Details of one of the memory cells MC are shown in FIG. 1.
When a sub-word line, e.g., a sub-word line SWL1, is activated and the memory cells MC to the left side of the sense amplifier blocks SA are selected, the memory cells to the right side of the sense amplifier blocks SA are not selected. And thus, noise generated in bit lines BL1 and BL2 (noise caused by a coupling capacitance) is different from noise generated in complementary bit lines BLB1 and BLB2. That is, a mismatch occurs between the coupling capacitances of the bit lines and the complementary bit lines.
Therefore, in the semiconductor memory device 5 having the open bit structure, a mismatch in the coupling capacitance may lead to an unstable sensing operation of the bit line sense amplifier with respect to the bit lines BL or the complementary bit lines BLB.
FIG. 2 illustrates the configuration of the bit line sense amplifier of FIG. 1. Referring to FIG. 2, the bit line sense amplifier includes a plurality of sense amplifier blocks SA1 through SAn, a plurality of NMOS sense amplifier drivers (hereinafter referred to as the “NSA drivers”) 10, and a PMOS sense amplifier driver (hereinafter referred to as the “PSA driver”) 20.
The sense amplifier blocks SA1 through SAn are arranged between memory cell regions MCA in which a plurality of memory cells are placed. The NSA drivers 10, each including an NMOS transistor, are distributed over a bit line sense amplifier region close to the bit line sense amplifier, in order to improve the sensing capability of NMOS sense amplifier NSA. For example, one NSA driver 10 may be placed for every two or more sense amplifier blocks. Each of the NSA drivers 10 is located between NMOS transistors that form a precharge unit PCH of one of the sense amplifier blocks SA1 through SAn, and an NMOS transistor that forms a second column selection unit CS2 of one of the sense amplifier block SA1, . . . , SAn.
The PSA driver 20 includes a PMOS transistor that is larger than the NMOS transistor of the NSA driver 10, and is located in a conjunction area CONJ between sub-word line driver regions SWD. In the sub-word line driver regions SWD, a sub-word line driver is located to drive sub-word lines connected to cell transistors of memory cells aligned in the memory cell regions MCA. Each of the sub-word lines is connected to a main word line via the sub-word line driver. A control circuit that controls the sub-word line drivers and the bit line sense amplifier is located in the conjunction region CONJ.
The first sense amplifier block SA1 includes a first column selection unit CS1, a PMOS sense amplifier PSA, the NMOS sense amplifier NSA, an equalization unit EQ, a precharge unit PCH, and a second column selection unit CS2.
The first column selection unit CS1 either connects the bit line BL to a local input/output (I/O) line LIO that is connected to a data I/O pin, or disconnects them from each other, in response to a signal transmitted via the first column selection line CSL1. The first column selection unit CS1 includes an NMOS transistor.
The PMOS sense amplifier PSA senses and amplifies a signal difference between the bit line BL and the complementary bit line BLB, in response to power source voltage VDD transmitted via a power source voltage supply line LA. The PMOS sense amplifier PSA includes a plurality of PMOS transistors. The PSA driver 20 applies the power source voltage VDD to the PMOS sense amplifier PSA via the power source voltage supply line LA, in response to a first sensing enable signal LAE.
The NMOS sense amplifier NSA senses and amplifies a signal difference between the bit line BL and the complementary bit line BLB, in response to ground voltage VSS applied via a ground voltage supply line LAB. The NMOS sense amplifier NSA includes a plurality of NMOS transistors. The NSA drivers 10 applies the ground voltage VSS to the NMOS sense amplifier NSA via the ground voltage supply line LAB, in response to a second sensing enable signal LABE. The NSA driver 10 is illustrated in greater detail in FIG. 3.
The equalization unit EQ is configured to equalize the voltage of the bit line BL with that of the complementary bit line BLB in response to a signal transmitted via a precharge/equalization signal line PEQ. The equalization unit EQ includes an NMOS transistor.
The precharge unit PCH is configured to precharge the voltages of the bit line BL and the complementary bit line to a precharge voltage (power source voltage VDD/2), in response to a signal transmitted via the precharge/equalization signal line PEQ. The precharge unit PCH includes a plurality of NMOS transistors. The precharge voltage is applied via a precharge voltage line VBL.
The second column selection unit CS2 either connects the complementary bit line BLB to a complementary local I/O line LIOB that is connected to the data I/O pin, or disconnects them from each other, in response to a signal transmitted via a second column selection line CSL2. The second column selection unit CS2 includes an NMOS transistor.
The elements of each of the second through nth sense amplifier blocks SA2 through SAn are the same as those of the first sense amplifier block SA1.
FIG. 3 illustrates a connection between the NSA driver 10 and the ground voltage supply line LAB, which are illustrated in FIG. 2. Referring to FIG. 3, the NSA driver 10 may be embodied as an NMOS transistor that operates in response to the second sensing enable signal LABE.
A source region of the NMOS transistor 10 is connected to the ground voltage line VSS (first metal line) via a first direct contact DC1. A drain region of the NMOS transistor 10 is connected to a second metal line M2 via a second direct contact DC2. Also, the second metal line M2 is connected to the ground voltage supply line LAB (first metal line) through a via VIA. The arrangement direction of the ground voltage line VSS is the same as that of the ground voltage supply line LAB.
The drain region of the NMOS transistor 10 is connected via the second metal line M2 because the NMOS transistor forming the NSA driver 10 is arranged in a small layout region located between the NMOS transistors forming the precharge unit PCH and the NMOS transistor forming the second column selection unit CS2, as illustrated in FIG. 2.
Since the NSA driver 10 is connected to the ground voltage supply line LAB through the second direct contact DC2, the second metal line M2, and the via VIA, the resistance between the NSA driver 10 and the ground voltage supply line LAB increases. Thus, the NSA driver 10 may not always be capable of stably applying the ground voltage VSS for a stable sensing operation of the NMOS sensing amplifier NSA. To counter this, the size, and thus the current capacity, for example, of the transistor of the NSA driver 10 may be increased, but then the size of the semiconductor memory chip may be increased.
FIG. 4 is a layout diagram of the sense amplifier block of FIG. 2. In FIG. 4, CS1L, PSAL, NSAL, PEQL, and CS2L respectively denote the layouts of the NMOS transistor that constitutes the first column selection unit CS1, the PMOS transistors PM1 and PM2 that constitute the PMOS sense amplifier PSA, the NMOS transistors NM1 and NM2 that constitute the NMOS sense amplifier NSA, the NMOS transistors that constitute the equalization unit EQ and the precharge unit PCH, and the NMOS transistor that constitutes the second column selection unit CS2.
In the layout CS1L of the first column selection unit CS1, a gate GATE and an active area ACT of the NMOS transistor that constitutes the first column selection unit CS1 are illustrated. The layouts of the other MOS transistors in the figure are illustrated in the same manner.
The NMOS transistor of the first column selection unit CS1, the NMOS transistors NM1 and NM2 of the NMOS sense amplifier NSA, the NMOS transistors of the equalization unit EQ and the precharge unit PCH, and the NMOS transistor of the second column selection unit CS2 are formed on a P-type substrate PSUB. In contrast, the PMOS transistors PM1 and PM2 of the PMOS sense amplifier PSA are formed in an N-type well NWELL in the P-type substrate PSUB.
As illustrated in FIG. 4, the MOS transistors that constitute the PMOS sense amplifier PSA and the NMOS sense amplifier NSA are asymmetrical with respect to a bit line BL and a complementary bit line BLB, and the MOS transistors of the equalization unit EQ and the precharge unit PCH are asymmetrical with respect to the bit line BL and the complementary bit line BLB since the MOS transistors are located on the right part of the layout of the sense amplifier block. Thus, the coupling capacitances of the bit line BL and the complementary bit line BLB that are generated when a data write operation or a data read operation of the semiconductor memory device is performed, are different from each other. Accordingly, the sensing operation of the bit line sense amplifier for a data write operation or a data read operation may be unstable.